Moore's Law of Real Estate : Gunnar Branson at TEDxNaperville

Steve Wozniak on Kurzweil's Singularity, Moore's Law, Wearable Tech, and...

HC25-K1: The Chip Design Game at the End of Moore's Law

Moore's Law

Is it the End for Moore's Law? - Computerphile

DRM Related VLSI interview questions

1. What are the difference between 45nm and 65nm routing rules? any new rule in the 45nm?
2. Why foundry define DRM, routing rules?
3. What is stack means? How many types of metal layers are in 65nm/45nm? Why metals are of different thickness?
4. Why thin metal are in lower position and thick metals are at upper position in a defined Stack?
5. What is the need of several types of metal layer in a design?
6. What do you mean by RDL layer? Why it requires?
7. How many types of routing? What is the sequence of that?
8. Power is routed first or clock is routed first ? and why?
9. what do you mean by notch rule? what is notch exactly (in terms of shape)?
10. Why we code routing rules?
11. What is stack VIA and why it requires?
12. Why foundry define min spacing rules/min width rules?
13. What do means by 65nm technology? Why it is saying 65nm?
14. In terms of foundry what are the main difference in 65nm and 45nm technology? (means why technology is changing continuously? explanations from the foundry point of view.)
15. What you think what are the challenges foundry face between two technology?
16. what do u mean by crosstalk?
17. How can you prevent this (crosstalk)?
18. what do u mean by grid and non grid routing? which one is preferable and why?
19. In magma tools , what is the concept behind sub grid?
20. What are the different types of Grids?
21. Why we use VIA array? Why not single large VIA in place of several via's?
22. What do you mean by VIA overhang? Why it is needed?
23. What do you mean by same grid spacing in VIAs?
24. What is shielding? How can U shield a clock rail?
25. The spacing between two single VIAs and spacing between via in VIA's array.. which one is smaller and why?
26. How many types of spacing rules?
27. How many types of width rules?
28. What is fat wire? Why rules are define separately for this?
29. How many layers are there in 130nm technology.
30. What is min area rules?
31. If the area of one metal layer is minimum from the min area rules then what should a designer do to prevent this?
32. Routing rules are dependent on the types of metal used. Is it true or false and why?
33. Why different types of metal layers (Al and Cu) are used in the design?
34. What are the different types of Pitch?
35. What do you mean by Pitch?
36. What is antenna rules? Why it define? Explain from the point of view of foundry also.
37. From where that accumulated charge come ?
38. How this charge effect a gate? and why?
39. How jumpers and diode prevent antenna violation?
40. Which type of diode is used to prevent antenna violation and how it works?
41. Where should be Jumper used?
42. What are the different types of antenna violation rules?
43. What is slotting rules?
44. Why it define?
45. How slots in the metal helps it?
46. What is density rules?
47. What is EM rules?
48. Why they are define?
49. How current density is dependent on temperature?
50. How many types of rule are there in EM section?
51. What is the significance of these rules from foundry point of view and from designer point of view?
52. What are the difference between average current density and RMS current density? OR How many types of current density and what are the difference between them?
53. Draw a diagram of CMOS. Explain different types of layers in it.
54. What do you mean by diffusion layers?
55. What is POD, NOD, Pwell, Nwell, N+,N++, P+, P++,Substrate, poly layer.
56. What is Oxidation, Lithography?
57. What is trench?
58. What is masking?
59. What is etching?

very nice and interesting book for VLSI initiators

https://drive.google.com/file/d/0Bx2vq0AOh9UUNWFkelFVSDBnZWs/edit?usp=sharing

Article 1 : Reason behind the innovation of scale integration

See,guys..VLSI or any SI upto date is basically used to converge electronics in characterized by reliability, low power dissipation, extremely low weight and volume, and low cost, coupled with an ability to cope easily with a high degree of sophistication and complexity and in particular the integrated circuit, has made possible the design of powerful and flexible processors which provide highly intelligent and adaptable devices for the user...

VLSI project on : " Design of High Speed Kogge-Stone Based Carry Select Adder "

Download here :

https://drive.google.com/file/d/0Bx2vq0AOh9UUTW80MTdOLWpELUE/edit?usp=sharing

Some of Famous RISC microprocessor

• 801

To prove that his RISC concept was sound,John Cocke created the 801 prototype micrroprocessor (1975). It was never marketed but plays a pivotal role in computer history,becoming the first RISC microprocessor.

• RISC 1 and 2 

The first"proper" RISC chips were created at Berkely Uinversity in 1985.

• ARM

One of the most well known RISC developers is cambridge vased advanced Research Machines (originally ACORN  RESEARCH  MACHINES). Their ARM aand Strong ARM  chips power the old Acorn Archimedes and the apple newton handwriting recognition systems.Since the unbundling of ARM from Acorn ,intel has invested a considerable amount of money in the company and has utilized the technology in their processor design. One of the main advantaged for the ARM is the price;its costs less than £10. If samsung had bought the Amiga in1994,they would possibly have used the chip to power the low-end Amigas.

Programing funda

Before start any complex logic to  program , keep this formula in mind.

this following equation is commonly used for expressing a computer's performance ability :

TIME\PROGRAM = [ TIME/CYCLE] x [CYCLE/INSTRUCTION] x [INSTRUCTION/PROGRAM]